Infineon’s SEMPER X1 tackles latency challenges of electric and smart vehicles

Infineon Technologies last week introduced the automotive industry’s first LPDDR flash memory to support the development of new E/E (electrical and electronic) systems for semi-autonomous vehicles. Safe, reliable and real-time code execution, which is essential for automotive area and domain control, is provided by the Infineon SEMPER X1 LPDDR Flash solution.

According to Infineon, the device enables 20 times faster random read transactions for real-time applications and performs eight times better than conventional NOR Flash memory. To call this type of performance improvement remarkable is not hyperbolic.

Typical NOR Flash memory is often referred to as non-volatile storage, which means that storage devices with this type of flash memory retain data without using a battery or other power source. This capability has enabled software-dependent cars to offer state-of-the-art functionality with improved safety and architectural flexibility.

Next-gen cars are computers on wheels

As I’ve observed in previous articles, modern cars have become computers on wheels over the past 20 years. Next-generation cars depend on advanced multi-core computers created using modern manufacturing techniques.

Because real-time intelligence and connectivity are required to satisfy the need for safety and reliability in autonomous driving scenarios, high-density embedded non-volatile memories are no longer a financially viable alternative. However, these sophisticated automotive real-time computers require more extraordinary performance than that offered by current memory solutions.

Infineon created SEMPER X1 with a proven LPDDR4 interface running at 3.2 Gb/second and a multi-bank architecture to meet the performance and density needs of domain and zone controllers.

Traditional safety-critical functions in a next-generation car (Source: Infineon Technologies)

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The resulting value proposition is quite compelling. Infineon combines flash memory with an LPDDR (Low Power Double Date Rate) interface to enable more spectacular performance and expandability than xSPI NOR flash to meet the new demands of automotive area designs. Infineon’s choice to use this interface is smart, given that the interface has been on the market for years and has a reputation for low-risk implementations.

From a vehicle perspective, the transition to software-defined vehicle architectures has caused a memory challenge for next-generation automotive designs. Traditional xSPI NOR Flash memory is inadequate for several reasons, cost being one of the main ones. SEMPER XI leverages the DRAM industry’s LPDDR interface method to meet the new computing requirements of the automotive industry.

Key automotive demands: increasing performance, density requirements

Next-generation semi-autonomous automobiles require more and more flash memory and faster performance. Cars have been moving towards zonal designs for some time with uncompromising real-time processing. These higher performance demands simply cannot be met by what ordinary NOR flash storage provides today.

The growing number of domain and zone controllers appearing in next-generation semi-autonomous vehicles must process massive volumes of real-time data while consolidating many security-critical operations.

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These area controllers have intense real-time computing needs. While these controllers send information to the main ECU (electronic control unit), these zonal controllers must also manage the steering, engine, and other critical safety functions.

Automotive area controllers are constantly being pushed to provide higher levels of performance to meet these real-time processing demands. A controller with built-in onboard memory simply cannot handle this high level of complex processing.

Faster access to necessary external flash

The processing demands of next-generation automotive designs have driven a move away from real-time processors with few processor cores and onboard flash memory. At a high level, it can reasonably be said that the evolution of semiconductor technology has caused a mismatch between processor and memory.

Given the cost pressures in the smart car and electric vehicle markets, adding on-board flash is not economically viable using today’s advanced semiconductor process nodes used by these processor solutions.

The reality is that fast, real-time multi-core processors, which run off external flash memory, are needed to meet the demands of next-generation automotive designs.

Automotive-qualified embedded flash technologies struggle with high cost (large die areas) and lack of scalability at advanced manufacturing nodes. Additionally, the industry needs additional flash memory to accommodate the growing size and complexity of code.

xSPI is not scalable and has run out of gas

All of these factors seem to have influenced Infineon’s role in the development of LPDDR Flash memory.

Infineon’s Vice President of Marketing and Applications, Sandeep Krishnegowda, made it clear that the company used high-level OEM feedback to help define the LPDDR memory category as the right solution to meet the growing need for capacity. real-time computing for code execution by multi-core processors. . This approach makes sense because fast random access is at the heart of LPDDR flash.

Undoubtedly, this method speeds up execution rates. According to Infineon, compared to a typical Octal (x8) xSPI NOR flash chip, using LPDDR flash provides an astonishing 20-fold increase in performance. Conversely, this performance boost is needed to scale from real-time computations to inside the CPU to those in external memory.

With its LPDDR interface, SEMPER X1 flash memory can provide data rates of up to 3.2 GB/second. Its multi-bank design enables over-the-air firmware changes without downtime, which is essential in autonomous driving scenarios. The device also includes enhanced error correction and other security measures, and is ISO 26262 ASIL-B compliant.

Other factors come into play in replacing xSPI with LPDDR flash.

First, xSPI, as a legacy interface, is not only too slow, but does not scale adequately from the perspective of future needs. This critical factor is also driving the demand for LPDDR flash. Additionally, xSPI devices currently on the market use a low-voltage complementary metal oxide semiconductor (LVCMOS) approach that cannot scale beyond 200 MHz, requiring a solution with higher bandwidth.

In this context, conventional Octal xSPI flash devices are not suitable for code execution because they cannot support today’s gigahertz multi-core processors.

Final Thoughts

Infineon’s SEMPER X1 is an essential step in this direction as it facilitates more complex motor control and real-time decision making enhanced by a memory architecture that can scale independently of the CPU.

This new class of non-volatile memory will be fascinating to observe as the ecosystem develops. My recent podcast with Krishnagowda provides an intriguing insight into what he believes to be the disruptive implications of this new announcement.

Infineon has been a bit cautious about which market categories beyond the automotive space LPDDR Flash memory might appeal to.

Linus Wong, Infineon’s director of product management for SEMPER X1, agrees that warehousing, security and medical applications can see huge interest in this new storage capability. “When we look at these secondary markets, it really comes down to the improved value proposition for (the usage patterns) that can leverage latency improvements measured in thousands of seconds,” he said.

Finally, it is significant that Infineon played a leading role in the industry by launching this new memory solution. The company’s gravitas, reputation for design excellence, and solid execution track record that’s crucial with next-generation, high-ASP cars are all tailwinds that favorably support the market’s acceptance of LPDDR flash memory.

According to Infineon, SEMPER X1 is currently being sampled, with commercial release expected sometime in 2024.